The present invention is related in general to the field of semiconductor devices and processes and more specifically to system and methods of reinforcing bond pads applying the same fine feature size design rules as for integrated circuits.
It is well known in semiconductor technology that bond pads on silicon integrated circuits can be damaged during wafer probing using fine-tip tungsten needles, further during conventional thermosonic wire bonding to aluminum metallization on the circuits, or during solder ball attachment in more recent technical developments. Mechanical loading and ultrasonic stresses applied by the tip of the bonding capillary to the bond pad are particularly suspect. When the damage is not apparent during the bonding process, the defects may manifest themselves subsequently by succumbing to thermo-mechanical stresses generated during plastic encapsulation, accelerated reliability testing, temperature cycling, and device operation. The damage appears in most cases as microcracks which may progress to fatal fractures in the underlying dielectric, as chip-outs of brittle or mechanically weak dielectric films, often together with pieces of metal or silicon, or as lifted ball bonds or delamination of metal layers.
Recent technological developments in the semiconductor industry tend to aggravate the problem. For instance, newer dielectric materials such as silicon-containing hydrogen silsesquioxane (HSQ) are being preferred due to their lower dielectric constant which helps to reduce the capacitance C in the RC time constant and thus allows higher circuit speed. Since the density and porosity of dielectric films affect the dielectric constant through absorption or desorption of water, films with these characteristics are introduced even when they are mechanically weaker. Films made of aerogels, organic polyimides, and parylenes fall into the same category. These materials are less dense and mechanically weaker than previous standard insulators such as the plasma-enhanced chemical vapor deposited dielectrics. This trend even affects stacks of dielectric layers such as alternating layers of plasma-generated tetraethylorthosilicate (TEOS) oxide and HSQ, or ozone TEOS oxide and HSQ. Since these material are also used under the bond pad metal, they magnify the risk of device failure by cracking.
In addition, the pitch of bond pads is being progressively more reduced to save valuable silicon real estate. Consequently, the bonding parameters have to become more aggressive to achieve stronger bonds in spite of smaller size. Bonding force and ultrasonic energy during bonding are being increased. Again, the risk of yield loss and lowered reliability is enhanced.
For conventional bond pad metallization processes, a solution to the aforementioned problems was disclosed in patent application Ser. No. 08/847,239, filed May 1, 1997, titled xe2x80x9cSystem and Method for Reinforcing a Band Padxe2x80x9d, assigned to Texas Instruments Incorporated. Some concepts and methods of this disclosure have been subsequently described in a publication entitled xe2x80x9cElimination of Bond-pad Damage through Structural Reinforcement of Intermetal Dielectricsxe2x80x9d by M. Saran et al. (Internat. Reliab. Physics Symp., March 1998). In essence, a mechanically strong metal structure is serving as reinforcement for the mechanically weak dielectric layer. The metal is deposited and then etched to form xe2x80x9creservoirsxe2x80x9d to be filled with the dielectric material, for example HSQ. For instance, the metal pattern thus formed may include grid-shaped or crucifix-shaped elements. The metal line widths and spacing are structured to confine much of the HSQ into the reservoirs while minimizing the area of each reservoir so that the HSQ layer is spared the direct mechanical impact of the bonding process.
Since HSQ is deposited by a spin-on process, the sizes of the reservoirs have to remain large enough to be filled controllably with the dielectric. This requirement is contrary to the industry trend for continued shrinking of all circuit feature sizes. Furthermore, the industry-wide trend towards smaller dimensions for increasing circuit speed brought the so-called damascene metallization process recently to wide acceptance. In this process flow, an insulator film is formed first; openings such as trenches are then etched into this film. Next, metal such as copper or aluminum is deposited to fill these openings. Whatever metal is deposited elsewhere on the surface, is removed by grinding and polishing, leaving only the metal embedded in the trenches. This process flow, however, is the inverse of the conventional process underlying the above cited patent application.
Wire bonding and solder ball flip-chip bonding over damascene metal pads are facing the same issues (transfer of mechanical and ultrasonic energies to the bond pads and risks of cracking weak dielectric layers) as in the case of conventional metallization. In addition, dielectric materials, even gels or foams, with lower dielectric constants are continually introduced in spite of their lowered mechanical strengths. This trend is driven not only circuit speed, but also by power dissipation and cross-talk, for instance in hand-held communication terminals.
An urgent need has, therefore, arisen for a reliable system and method for fine-pitch reinforcement of bond pads using the damascene metallization process. The system and method should provide stress-free, simple and low-cost bond pads suitable for flexible, tolerant bonding processes even when the bond pads are situated above one or more structurally and mechanically weak dielectric layers. The system and method should be applicable to a wide spectrum of design, material and process variations, leading to improved process yield and device reliability. Preferably, these innovations should be accomplished using the installed process and equipment base so that no investment in new manufacturing machines is needed.
In accordance with the present invention, a bond pad reinforcing system and method are provided which are compatible with the damascene metallization process and permit fine-pitch designs of the reinforcing system comparable to the feature sizes of the integrated circuit components. The system eliminates or substantially reduces the disadvantages associated with prior apparatus and methods.
The invention utilizes the sequence of processing steps applied to producing the integrated circuit. For the reinforcing structure, the dielectric layers are deposited first and the trenches etch with design rules typical for integrated circuit features. These fine-pitch openings are filled with metal such that metal and dielectrics are discretely confined to their respective regions.
It is an object of the invention to advance the process and operation reliability of semiconductor wire bonded and solder attached assemblies by structurally reinforcing the bond pad metallizations even for multi-level architectures under the bond pads.
Another object of the invention is to eliminate restrictions on the size of the dielectric pattern, thus minimizing the risks of inflicting cracking damage even to very brittle dielectrics.
Another object of the invention is to provide design concepts and process methods which are flexible so that they can be applied to several families of products, and are general, so that they can be applied to several generations of products.
Another object of the present invention is to provide a low-cost and high speed process for fabrication and assembly.
Another object of the invention is to use only designs and processes already employed in the fabrication of integrated circuit devices, thus avoiding the cost of new capital investment and using the installed fabrication equipment base.
These objects have been achieved by the teachings of design concepts and process flow suitable for mass production. Various modifications have been successfully employed to satisfy product geometry""s and material selections.
In one embodiment of the invention, a reinforcing patterned system for a bond pad is disposed in at least one dielectric layer or at least one dielectric stack of multiple dielectric layers disposed under the bond pad. A reinforcing patterned structure is disposed in at least one dielectric stack.
In another embodiment of the invention the reinforcing patterned structure may be a joined or interconnected structure. In another embodiment of the invention, the reinforcing patterned structure may comprise disjoined or non-interconnected and repeating elements.
In yet another aspect of the invention, a method for reinforcing a bond pad in a semiconductor integrated circuit includes the steps of forming a first dielectric layer, patterning the dielectric layer in a predetermined area into a predetermined pattern having a plurality of vacant areas, forming a metal layer above the patterned first dielectric layer, filling the vacant areas in the dielectric layer, removing the metal except for the filled vacant areas, whereby a uniformly flat surface is formed, and forming a second dielectric layer above the uniformly flat surface. A bond pad is then formed on the second dielectric layer.
A technical advantage of the present invention is the improved structural integrity of bond pads for the preferred damascene metallization process, with no unusual restrictions on design rules for dimensions of the reinforcing structure. Forces exerted during multiprobe testing and the bonding process do not damage the bond pad and underlying structures. These technical advantages are possible without changing probing or bonding parameters, which may otherwise decrease the process throughput and yield. The result is a more reliable device and diminished failure rates.